Location :

Pan India

Experiences :

4 to 12 Years

Key Skills :

Design for Test (DFT), Scan Insertion, ATPG, JTAG, BIST, Verilog, VHDL, Cadence Modus/Xcelium, , Synopsys DFTMAX/TetraMax and Mentor Graphics Tessent

Roles and Responsibilities :

• Develop and implement Design for Test (DFT) strategies for ASIC designs.
• Perform scan insertion, Automatic Test Pattern Generation (ATPG), and Built-In Self-Test (BIST) implementation.
• Work with JTAG and boundary scan techniques.
• Collaborate with design and verification teams to integrate DFT features into the design.
• Utilize CAD tools such as Cadence and Synopsys for DFT implementation and verification.
• Debug and resolve DFT-related issues during the design and testing phases.
• Ensure testability and manufacturability of the design, meeting industry standards and specifications.
• Document DFT methodologies and provide clear reports to the design team.