Location :

Pan India

Experiences :

4 to 12 Years

Key Skills :

Static Timing Analysis (STA), Timing Closure, Synopsys PrimeTime, Cadence Tempus, Scripting (TCL, Perl), Verilog, VHDL

Roles and Responsibilities :

• Perform Static Timing Analysis (STA) to ensure timing closure of ASIC designs.
• Utilize tools such as Synopsys PrimeTime and Cadence Tempus for timing analysis.
• Identify and resolve timing violations, working closely with design and verification teams.
• Develop and maintain timing constraints and scripts for STA.
• Collaborate with cross-functional teams to optimize design performance and meet timing requirements.
• Document timing analysis results and provide clear reports to the design team.
• Stay updated with the latest STA methodologies and tools.